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w wm8782 24-bit, 192khz stereo adc wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews production data, april 2010, rev 4.7 copyright ? 2010 wolfson microelectronics plc description the wm8782 is a high performance, low cost stereo audio adc designed for recordable media applications. the device offers stereo line level inputs along with two control input pins (format, iwl) to allow operation of the audio interface in three industry standard modes. an internal op-amp is integrated on the front end of the chip to accommodate analogue input signals greater than 1v rms . the device also has a high pass filter to remove residual dc offsets. wm8782 offers master or slave mode clocking schemes. a control input pin m/s is used to allow slave mode operation or master mode operation. a stereo 24-bit multi- bit sigma-delta adc is used with 128x, 64x or 32x over- sampling, according to sample rate. digital audio output word lengths from 16-24 bits and sampling rates from 8khz to 192khz are supported. the device is a hardware controlled device and is supplied in a 20-lead ssop package. the device is available over a functional temperature range of -40 ? c to +85 ? c features ? snr 100db (?a? weighted @ 48khz) ? thd -93db (at ?1db) ? sampling frequency: 8 ? 192khz ? master or slave clocking mode ? system clock (mclk): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs - audio data interface modes ? 16-24 bit i 2 s, 16-24 bit left, 16-24 bit right justified ? supply voltages - analogue: 2.7 to 5.5v - digital core: 2.7v to 3.6v ? 20-lead ssop or 20-lead tssop package ? accelerated lifetime screened devices available. applications ? recordable dvd players ? personal video recorders ? stb ? studio audio processing equipment ? automotive block diagram
wm8782 production data w pd, april 2010, rev 4.7 2 table of contents description ....................................................................................................... 1 ? features ............................................................................................................ 1 ? applications ..................................................................................................... 1 ? block diagram ................................................................................................ 1 ? table of contents ......................................................................................... 2 ? pin configuration .......................................................................................... 3 ? ordering information .................................................................................. 3 ? pin description ................................................................................................ 4 ? absolute maximum ratings ........................................................................ 5 ? thermal performance ................................................................................. 5 ? recommended operating conditions ..................................................... 6 ? electrical characteristics ..................................................................... 6 ? terminology ............................................................................................................... 7 ? signal timing requirements ...................................................................... 8 ? system clock timing ................................................................................................ 8 ? audio interface timing ? master mode ............................................................ 8 ? audio interface timing ? slave mode ................................................................ 9 ? slave mode mclk / bclk timing ........................................................................... 10 ? device description ...................................................................................... 11 ? introduction ............................................................................................................ 11 ? adc ........................................................................................................................... ..... 11 ? adc digital filter ................................................................................................... 11 ? digital audio interface ........................................................................................ 12 ? power on reset ...................................................................................................... 15 ? digital filter characteristics .............................................................. 17 ? adc filter responses ........................................................................................... 17 ? adc high pass filter .............................................................................................. 18 ? applications information ........................................................................ 19 ? recommended external components ............................................................ 19 ? recommended external components values ............................................. 19 ? package dimensions .................................................................................... 20 ? 20 pin ssop ................................................................................................................. 2 0 ? 20 pin tssop ............................................................................................................... 21 ? important notice ......................................................................................... 21 ? address: ..................................................................................................................... 21 ?
production data wm8782 w pd, april 2010, rev 4.7 3 pin configuration 1 mclk 2 3 vrefgnd 4 5 vrefp 6 7 avdd 8 ainr 9 agnd 10 ainopr ainopl com ainl m/s bclk fsampen iwl lrclk dgnd dout dvdd vmid format 11 12 13 14 15 16 17 20 19 18 ordering information device temperature range package moisture sensitivity level peak soldering temperature wm8782seds/v -40 ? c to +85 ? c 20-lead ssop (pb-free) msl2 260 o c wm8782seds/rv -40 ? c to +85 ? c 20-lead ssop (pb-free, tape and reel) msl2 260 o c note: reel quantity = 2,000
wm8782 production data w pd, april 2010, rev 4.7 4 pin description pin no. name type description 1 mclk digital input master clock 2 dout digital output adc digital audio data 3 lrclk digital input / output audio interface left / right clock 4 dgnd supply digital negative supply 5 dvdd supply digital positive supply 6 bclk digital input / output audio interface bit clock 7 iwl digital tristate input word length 0 = 16 bit 1 = 20 bit z = 24 bit 8 fsampen digital tristate input fast sampling rate enable 0 = 48khz 1= 96kkhz z= 192khz 9 format digital tristate input audio mode select 0 = rj 1 = lj z = i2s 10 vmid analogue output mid rail voltage decoupling capacitor 11 vrefgnd supply negative supply and substrate connection 12 vrefp analogue output positive reference voltage decoupling pin; 10uf external decoupling 13 avdd supply analogue positive supply 14 agnd supply analogue negative supply and substrate connection 15 ainopr analogue output right channel internal op-amp output 16 ainr analogue input right channel input 17 com analogue input common mode high impedance input should be set to midrail. 18 ainopl analogue output left channel internal op-amp output 19 ainl analogue input left channel input 20 m/s digital input interface mode select 0 = slave mode (128fs, 192fs, 256fs, 384fs, 512fs, 768fs) 1 = master mode (256fs, 128fs) (fs=word clock frequency)
production data wm8782 w pd, april 2010, rev 4.7 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional oper ating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper es d precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j- std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level is specified in ordering information. condition min max digital supply voltage -0.3v +4.5v analogue supply voltage -0.3v +7v voltage range digital inputs dgnd -0.3v dvdd + 0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v ambient temperature (supplies applied) -55 ? c +125 ? c storage temperature -65 ? c +150 ? c pb free package body temperature (reflow 10 seconds) +260 ? c package body temperature (soldering 2 minutes) +183 ? c notes: 1. analogue and digital grounds must always be within 0.3v of each other. thermal performance parameter symbol test conditions min typ max unit thermal resistance ? junction to ambient r ja 81 see note 1 c/w notes: 1. figure given for package mounted on 4-layer fr4 accord ing to jesd51-7. (no forced air flow is assumed). 2. thermal performance figures are estimated.
wm8782 production data w pd, april 2010, rev 4.7 6 recommended operating conditions parameter symbol test conditions min typ max unit digital supply range dvdd wm8782seds, wm8782seds/r 2.7 3.6 v analogue supply range avdd wm8782seds, wm8782seds/r 2.7 5.5 v ground dgnd,agnd 0 v operating temperature range t a wm8782seds, wm8782seds/r -40 +85 ? c notes: 1. digital supply dvdd must never be more than 0.3v greater than avdd. electrical characteristics test conditions dvdd = 3.3v, avdd = 5.0v, t a = +25 o c, 1khz signal, a-weighted, fs = 48khz, mclk = 256fs, 24-bit audio data, slave mode unless otherwise stated. parameter symbol test conditions min typ max unit adc performance ? wm8782seds, wm8782seds/r (+25 ? c) full scale input signal level (for adc 0db input) 1.0 v rms input resistance, using recommended external resistor network on p22. 10 k ? input capacitance 20 pf signal to noise ratio (see terminology note 1,2,4) snr weighted, @ fs = 48khz 93 100 db unweighted, @ fs = 48khz 98 db weighted, @ fs = 48khz, avdd = 3.3v 98 db signal to noise ratio (see terminology note 1,2,4) snr weighted, @ fs = 96khz 98 db unweighted, @ fs = 96khz 98 db weighted, @ fs = 96khz avdd = 3.3v 98 db total harmonic distortion thd 1khz, -1db full scale @ fs = 48khz -93 db 1khz, -1db full scale @ fs = 96khz -93 db 1khz, -1db full scale @ fs = 192khz -92 db dynamic range dnr -60dbfs 93 100 db channel separation (see terminology note 4) 1khz input 90 db channel level matching 1khz signal 0.1 db channel phase deviation 1khz signal 0.0001 degree power supply rejection ratio psrr 1 khz 100mvpp, applied to avdd, dvdd 50 db
production data wm8782 w pd, april 2010, rev 4.7 7 test conditions dvdd = 3.3v, avdd = 5.0v, t a = +25 o c, 1khz signal, a-weighted, fs = 48khz, mclk = 256fs, 24-bit audio data, slave mode unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels (ttl levels) input low level v il 0.8 v input high level v ih 2.0 v input leakage current ? digital pad -1 0.2 +1 a input leakage current ? digital tristate input (note 3) 85 a input capacitance 5 pf output low v ol i ol =1ma 0.1 x dvdd v output high v oh i oh = -1ma 0.9 x dvdd v analogue reference levels midrail reference voltage vmid avdd to vmid and vmid to vrefn ?4% avdd/2 +4% v potential divider resistance r vmid 70 k ? buffered reference voltage vrefp ?4% avdd/2 +4% v vref source current i vref 5 ma vref sink current i vref 5 ma supply current analogue supply current avdd = 5v 26 ma digital supply current dvdd = 3.3v 5 ma power down 0.5 ma notes: 1. all performance measurements are done with a 20khz low pass filter, and where noted an a-weight filter. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although this is not audible, it may affect dynamic specification values. 2. vmid is decoupled with 10uf and 0.1uf capacitors cl ose to the device package. smaller capacitors may reduce performance. 3. this high leakage current is due to the topology of the instate pads. the pad input is connected to the midpoint of an internal resistor string to pull input to vmid if undriven. terminology 1. signal-to-noise ratio (db) ? ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, over a 20hz to 20khz bandwidth. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) ? dr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) ? thd+n is a ratio, of the rm s values, of (noise + distortion)/signal. 4. channel separation (db) ? also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other.
wm8782 production data w pd, april 2010, rev 4.7 8 signal timing requirements system clock timing figure 1 system clock timing requirements test conditions dvdd = 3.3v, dgnd = 0v, t a = +25 o c, fs = 48khz, slave mode, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit system clock timing information mclk system clock pulse width high t mclkl 11 ns mclk system clock pulse width low t mclkh 11 ns mclk system clock cycle time t mclky 28 ns mclk duty cycle t mclkds 40:60 60:40 table 1 master clock timing requirements audio interface timing ? master mode figure 2 digital audio data timing ? master mode (see control interface) test conditions dvdd = 3.3v, dgnd = 0v, t a = +25 o c, master mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information lrclk propagation delay from bclk falling edge t dl 0 10 ns dout propagation delay from bclk falling edge t dda 0 10 ns table 2 digital audio data timing ? master mode
production data wm8782 w pd, april 2010, rev 4.7 9 audio interface timing ? slave mode figure 3 digital audio data timing ? slave mode test conditions dvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns lrclk set-up time to bclk rising edge t lrsu 10 ns lrclk hold time from bclk rising edge t lrh 10 ns dout propagation delay from bclk falling edge t dd 0 10 ns table 3 digital audio data timing ? slave mode note: lrclk should be synchronous with mclk.
wm8782 production data w pd, april 2010, rev 4.7 10 slave mode mclk / bclk timing mclk 1 mclk 2 bclk v _low a b c d keep-out area for mclk/bclk relationship v _low v _hi figure 4 mclk / bclk prohibited timing relationship in slave mode timing time (ns) description a 9 mclk falling edge to bclk falling edge keep-out window b 4 c 9 mclk rising edge to bclk falling edge keep-out window d 4 table 4 prohibited area timings in slave mode operation, there are two windows where the bclk falling edge relative to the mclk falling/rising edge is not allowed, as defined in figure 4 and table 4. any device with clocks operating in this area may cause incorrect operation of the adc, as detailed in wtr0444. this specification is guaranteed by design rather than test, and the timings are related to the switching level of the mclk and bclk pads. simulation has shown the switching level range for both the mclk and bclk pads across process, voltage and temperature to be as per the table below. switching level min (v) max (v) v _low 1.1 1.4 v _hi 1.3 1.6 table 5 simulated switching area range if the above timing constraints cannot be met in slave mode, it is recommended that wm8782a silicon is used in place of wm8782.
production data wm8782 w pd, april 2010, rev 4.7 11 device description introduction the wm8782 is a stereo 24-bit adc designed for demanding recording applications such as dvd recorders, studio mixers, pvrs, and av amplifiers . the wm8782 consists of stereo line level inputs, followed by a sigma-delta modulator and digital filtering. the device offers stereo line level inputs along with two control input pins (format, iwl) to allow operation of the audio interface in three industry standard modes (left justified, right justified or i 2 s) . an internal op-amp is integrated on the front end of the chip to accommodate analogue input signals greater than 1v rms . the device also has a high pass filter to remove residual dc offsets. the wm8782 offers master or slave mode clocking schemes. a control input pin m/s is used to allow slave mode or master mode operation. the wm8782 supp orts master clock rates from 128fs to 768fs and digital audio output word lengths from 16-24 bits. sampling rates from 8khz to 192khz are supported, delivering high snr operating with 128x, 64x or 32x over-sampling, according to the sample rate. the line inputs are biased internally through the operational amplifier to v mid . adc the wm8782 uses a multi-bit over sampled sigma-delta adc. a single channel of the adc is illustrated in figure 5. lin/rin analog integrator multi bits to adc digital filters figure 5 multi-bit oversampling sigma delta adc schematic the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. the adc full scale input is 1.0v rms at avdd = 5.0 volts. any input voltage greater than full scale will possibly overload the adc and cause distortion. note that the full scale input has a linear relationship with avdd. the internal op-amp and appr opriate resistors can be used to reduce signals greater than 1vrms before they reach the adc. the adc filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the adc to the correct sampling frequency to be output on the digital audio interface. adc output phase in the input to output data-path, the digital output data dout, is a phase inverted representation of the analogue input signal. adc digital filter the adc digital filters contain a digital high pass fil ter. the high-pass filter response detailed in digital filter characteristics. the operation of the high pass filter removes residual dc offsets that are present on the audio signal. .
wm8782 production data w pd, april 2010, rev 4.7 12 digital audio interface the digital audio interface uses three pins: ? dout: adc data output ? lrclk: adc data alignment clock ? bclk: bit clock, for synchronisation the digital audio interface takes the data from the inter nal adc digital filters and places it on dout and lrclk. dout is the formatted digital audio data stream output from the adc digital filters with left and right channels multiplexed together. lrclk is an alignment clock that controls whether left or right channel data is present on the dout line. dout and lrclk are synchronous with the bclk signal with each data bit transition signified by a bclk high to low transition. dout is always an output. bclk and lrclk maybe an inputs or outputs depending whether the device is in master or slave mode. (see master and slave mode operation, below). three different audio data formats are supported: ? left justified ? right justified ? i 2 s master and slave mode operation the wm8782 can be configured as either a master or slave mode device. as a master device the wm8782 generates bclk and lrclk and thus controls sequencing of the data transfer on dout. in slave mode, the wm8782 responds with data to clocks it receives over the digital audio interface. the mode can be selected by setting the ms input pin (see table 6 master/slave selection below). master and slave modes are illustrated below. figure 6 master mode figure 7 slave mode pin description m/s master/slave selection 0 = slave mode 1= master mode table 6 master/slave selection audio interface control the input word length and audio format mode can be selected by using iwl and format pins. pin description iwl word length 0 = 16 bit 1 = 20 bit z = 24 bit format audio mode select 0 = rj 1 = lj z = i2s table 7 audio data format control
production data wm8782 w pd, april 2010, rev 4.7 13 audio data formats in left justified mode, the msb is available on the first rising edge of bclk following an lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. figure 8 left justified audio interface (assuming n-bit word length) in right justified mode, the lsb is available on the last rising edge of bclk before an lrclk transition. all other bits are transmitted befor e (msb first). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each lrclk transition. figure 9 right justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following an lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 10 i 2 s audio interface (assuming n-bit word length)
wm8782 production data w pd, april 2010, rev 4.7 14 master clock and audio sample rates in a typical digital audio system there is only one c entral clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio system?s master clock (mclk). the external master sy stem clock can be applied directly through the mclk input pin. in a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the adc. the master clock is used to operate the digital filters and the noise shaping circuits. the wm8782 supports master clocks of 128fs, 192fs, 256fs, 384fs , 512fs and 768fs, where fs is the audio sampling frequency (lrclk). in slave mode, the wm8782 automatically detects the audio sample rate. in master mode, lrclk is generated for rate 256fs, unless the user changes this to 128fs using the fsampen pin = z (see table 9 below). bclk is also generated in master mode. bclk=mclk/4 for 256fs, and bclk=mclk/2 for 128fs. table 8 shows the common mclk frequencies for different sample rates. sampling rate (lrclk) master clock frequency (mhz) 128fs 192fs 256fs 384fs 512fs 768fs 8khz 1.024 1.536 2.048 3.072 4.096 6.144 16khz 2.048 3.072 4.096 6.144 8.192 12.288 32khz 4.096 6.144 8.192 12.288 16.384 24.576 44.1khz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 48khz 6.144 9.216 12.288 18.432 24.576 36.864 96khz 12.288 18.432 24.576 36.864 - - 192khz 24.576 36.864 - - - - table 8 master clock frequency selection in slave mode, the wm8782 has a master detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). if there is a greater than 32 clocks error the interface sets itself to the highest rate available (768fs). there must be a fixed number of mclks per lrclk, although the wm8782 is tolerant of phase variations or jitter on these clocks. fsampen the fsampen pin controls the over sampling rate of the adc. the wm8782 can operate at sample rates from 8khz to 192khz. the wm8782 uses a sigma-delta modulator that operates at an optimal frequency of 6.144mhz. by default the wm8782 generates the adc frequency at 128xosr. at fs=48khz, the adc frequency is 128xosr = 128x48khz = 6.144mhz. if fs=96khz, the fsampen pin must be set to 1. in this case, the adc frequency is 64xosr = 64x96khz = 6.144mhz. if fs=192khz, the fsampen pin must be set to z. in this case, the adc frequency is 32xosr = 32x192khz = 6.144mhz. it is recommended that the above settings are used for both master and slave mode. pin description m/s master/slave selection 0 = slave mode (128fs, 192fs, 256fs, 384fs, 512fs, 768fs) 1= master mode (256fs, 128fs when fsampen=z) fsampen fast sampling rate enable 0 = 48ken (128x osr) 1= 96ken (64x osr) z= 192ken (32x osr) table 9 master/slave and sampling rate enable selection
production data wm8782 w pd, april 2010, rev 4.7 15 power down control the wm8782 can be powered down by stopping mclk. power down mode using mclk is entered after 65536/fs clocks. on power-up, the wm8782 applies the power-on reset sequence described below. when mclk is stopped dout is forced to zero. power on reset figure 11 power supply timing requirements ? power-on figure 12 power supply timing requirements ? power-down
wm8782 production data w pd, april 2010, rev 4.7 16 test conditions avdd = 5v, dvdd = 3.3v, agnd = dgnd = 0v, t a = +25c parameter symbol test conditions min typ max unit power supply input timing information dvdd level to activate por ? power on v pora measured from dgnd 0.7 v avdd level to activate por ? power on v pora measured from agnd 0.7 v vmid level to activate por ? power on v pora measured from agnd 0.7 v dvdd level to release por ? power on (see notes 1 and 2) v porr measured from dgnd dvdd min v avdd level to release por ? power on (see notes 1 and 2) v porr measured from agnd avdd min v vmid level to release por ? power on (see notes 1 and 2) v porr measured from agnd 1 v por active period (see notes 1 and 2) t por measured from por active to por release 30 (note 6) defined by dvdd/avdd/ vmid rise time ? s dvdd level to activate por ? power off (see note 5) v por_off measured from dgnd 0.8 v avdd level to activate por ? power off (see note 5) v por_off measured from agnd 0.8 v vmid level to activate por ? power off (see note 5) v por_off measured from agnd 0.7 v power on ? por propagation delay through device t pon measured from rising edge of por 30 ? s power down ? por propagation delay through device t poff measured from falling edge of por 30 ? s notes: 1. por is activated when dvdd or avdd or vmid reach their stated v pora level (figure 11) 2. por is only released when dvdd and avdd and vmid have all reached their stated v porr levels (figure 11). 3. the rate of rise of vmid depends on the rate of rise of avdd, the internal 50k ? resistance and the external decoupling capacitor. typical tolerance of 50k resistor can be taken as +/-20%. 4. if avdd, dvdd or vmid suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below v por_off, ), then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. 5. the chip will enter reset at power down when avdd or dvdd or vmid falls below v por_off . this may be important if the supply is turned on and off frequently by a power management system. 6. the minimum t por period is maintained even if dvdd, avdd and vmid have zero rise time. this specification is guaranteed by design rather than test.
production data wm8782 w pd, april 2010, rev 4.7 17 digital filter characteristics the wm8782 digital filter characteristics scale with sample rate. parameter test conditions min typ max unit adc sample rate (single rate ? 48hz typically) passband +/- 0.01db 0 0.4535fs -6db 0.4892fs passband ripple +/- 0.01 db stopband 0.5465fs stopband attenuation f > 0.5465fs -65 db group delay 22 fs adc sample rate (dual rate ? 96khz typically) passband +/- 0.01db 0 0.4535fs -6db 0.4892fs passband ripple +/- 0.01 db stopband 0.5465fs stopband attenuation f > 0.5465fs -65 db group delay 22 fs table 10 digital filter characteristics adc filter responses -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 13 digital filter frequency response figure 14 adc digital filter ripple
wm8782 production data w pd, april 2010, rev 4.7 18 adc high pass filter the wm8782 has a digital highpass filter to remove dc offsets. the filter response is characterised by the following polynomial. figure 15 adc highpass filter response 1 - z -1 1 - 0.9995z -1 h(z) = -15 -10 -5 0 0 0.0005 0.001 0.0015 0.002 response (db) frequency (fs)
production data wm8782 w pd, april 2010, rev 4.7 19 applications information recommended external components figure 16 external components diagram recommended external components values component reference suggested value description c1 and c8 10 ? f de-coupling for dvdd and avdd c2 and c7 0.1 ? f de-coupling for dvdd and avdd c5 and c6 10 ? f analogue input ac coupling caps r1 10k ? current limiting resistors r2 and r5 10k ? internal op-amp input resistor r3 and r6 5k ? internal op-amp feedback resistor r4 3.3k ? common mode resistor c4 0.1 ? f reference de-coupling capacitors for vmid pin c3 10 ? f c9 0.1 ? f reference de-coupling capacitors for vrefp pin c10 10 ? f table 11 external components description the above table 11 shows resistor values which will give a gain of 0.5. this assumes an input signal of 2vrms to c4 and c5.
wm8782 production data w pd, april 2010, rev 4.7 20 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ae. refer to this specification for further details. dm0015.c ds: 20 pin ssop (7.2 x 5.3 x 1.75 mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- ----- a 2 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 d 6.90 7.20 7.50 e 0.65 bsc e 7.40 7.80 8.20 5.00 5.30 5.60 l 0.55 0.75 0.95 ? ref: a a2 a1 seating plane -c- 0.10 c 10 1 d 11 20 e b e1 e - jedec.95, mo 150 0 o 4 o 8 o e 1 l 1 1.25 ref ? c l gauge plane 0.25 l 1

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